• DocumentCode
    43076
  • Title

    Fast and Effective Placement Refinement for Routability

  • Author

    Yanheng Zhang ; Chu, Chris

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
  • Volume
    21
  • Issue
    9
  • fYear
    2013
  • fDate
    Sept. 2013
  • Firstpage
    1751
  • Lastpage
    1756
  • Abstract
    In this brief, we propose congestion refinement of placement (CROP) for improving the congestion of mixed-size placement solutions. CROP consists of a congestion-driven module shifting technique and a congestion-driven detailed placement (CDDP) technique. The shifting technique is proposed for better allocation of routing resources. We shift modules based on the shifting of G-cell boundaries. Shifting in each direction can be formulated as a linear program (LP) for resizing each cell in the global routing grid (i.e., G-cell). We degenerate and solve the LP by a very efficient longest path computation. Then the CDDP technique is proposed for distributing the routing demands better. Congestion reduction is realized by weighting the half-perimeter wirelength with the congestion factor during detailed placement. Theoretically, our tool is capable of handling most mixed-size placement benchmarks with movable and/or fixed macro (FM) blocks. In order to better analyze its performance, the ISPD-GR benchmark suite (ISPD05/06 derived global routing benchmarks) with FM modes is developed. The experimental results show that CROP effectively alleviates congestion for unroutable placement solutions in short runtimes for different placers.
  • Keywords
    VLSI; integrated circuit design; linear programming; network routing; CDDP technique; G-cell boundary shifting; ISPD-GR benchmark suite; ISPD05-06 derived global routing benchmark; LP formulation; VLSI design flow; congestion factor; congestion reduction; congestion refinement-of-placement; congestion-driven detailed placement technique; congestion-driven module shifting technique; fixed macroblock; global routing grid; half-perimeter wirelength; linear program; mixed-size placement solution congestion; movable macroblock; routability; routing demand distribution; routing resource allocation; Agriculture; Benchmark testing; Frequency modulation; Routing; Runtime; Very large scale integration; White spaces; Congestion; physical design; placement; routing;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2012.2214408
  • Filename
    6302222