Design of the clock recovery circuit with a phase-locked loop for 40 Gb/s optical receivers

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of a preamplifier, a nonlinear circuit with diodes, a bandpass filter and a clock amplifier. When a 40 Gb/s signal of 0 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -2 dBm output power. The implemented clock recovery circuit is to be used for the input of a phase-locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.