DocumentCode
43388
Title
Fast weighted bit flipping algorithm for higher-speed decoding of Low-Density Parity-Check codes
Author
Kexiang Ma ; Yongzhao Li ; Hailin Zhang
Author_Institution
Nat. Key Lab. on ISN, Xidian Univ., Xi´an, China
Volume
10
Issue
9
fYear
2013
fDate
Sept. 2013
Firstpage
114
Lastpage
119
Abstract
Because of the speed limitation of the conventional bit-selection strategy in the existing weighted bit flipping algorithms, a high-speed Low-Density Parity-Check (LDPC) decoder cannot be realised. To solve this problem, we propose a fast weighted bit flipping algorithm. Specifically, based on the identically distributed error bits, a parallel bit-selection method is proposed to reduce the selection delay of the flipped bits. The delay analysis demonstrates that, the decoding speed of LDPC codes can be significantly improved by the proposed algorithm. Furthermore, simulation results verify the validity of the proposed algorithm.
Keywords
parity check codes; LDPC codes; LDPC decoder; bit selection strategy; delay analysis; distributed error bits; fast weighted bit flipping algorithm; flipped bits; higher speed decoding; low density parity check codes; low density parity check decoder; parallel bit selection method; selection delay; Algorithm design and analysis; Decoding; Delays; Iterative decoding; Velocity control; LDPC; partially parallel; pipelined; weighted bit flipping;
fLanguage
English
Journal_Title
Communications, China
Publisher
ieee
ISSN
1673-5447
Type
jour
DOI
10.1109/CC.2013.6623509
Filename
6623509
Link To Document