Performance and power analysis of asynchronous pipeline design methods

Author

Gholipour, M. ; Shojaee, K. ; Khademzadeh, A. ; Afzali-Kusha, Ali ; Nourani, M.

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ., Iran

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

409

Lastpage

412

Abstract

In this paper, ten asynchronous pipeline styles are studied and compared. These include GasP, MOUSETRAP, IPCMOS, LP_SR2/1, LP_HC, STFB, LDA, LP2/1, RSPCFB and NCL. The first five designs are based on bundled-data (BD) category while the last five are based on data-driven (DD) category. Analytical expressions for the throughput and the latency of the asynchronous styles are presented. A 4-bit 4-stage FIFO circuit based on each style is designed and simulated utilizing HSPICE with a 0.18 μm CMOS technology. The simulation results are then used to compare the FIFOs in terms of throughput, latency, power dissipation and transistor count.

Keywords

CMOS logic circuits; SPICE; asynchronous circuits; circuit simulation; integrated circuit design; integrated circuit modelling; logic design; pipeline processing; 0.18 micron; CMOS technology; FIFO circuit design; FIFO circuit simulation; GasP method; HSPICE; IPCMOS method; LDA method; LP2/1 method; LP_HC method; LP_SR2/1 method; MOUSETRAP method; NCL method; RSPCFB method; STFB method; asynchronous pipeline design method; bundled data category; data driven category; performance analysis; power analysis; power dissipation; CMOS technology; Circuit simulation; Delay; Design methodology; Linear discriminant analysis; Performance analysis; Pipelines; Power dissipation; Strontium; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on

Print_ISBN

0-7803-8656-6

Type

conf

DOI

10.1109/ICM.2004.1434600

Filename

1434600