DocumentCode :
435690
Title :
Challenges and key potential technological innovations for scaling MOSFETS through the end of the roadmap
Author :
Zeitzoff, Peter M.
Author_Institution :
Int. SEMATECH, Austin, TX, USA
Volume :
1
fYear :
2004
fDate :
18-21 Oct. 2004
Firstpage :
20
Abstract :
The overall trends and challenges in logic MOSFET scaling are discussed from the perspective of the 2003 International Technology Roadmap for Semiconductors. Critical scaling challenges include gate leakage current and polysilicon gate depletion, difficulty in controlling short channel effects, etc. To address these, key innovations include high-k gate dielectric, metal gate electrode, strained silicon channel for enhanced mobility, and eventually, non-classical CMOS devices (e.g.. FinFETs).
Keywords :
MOSFET; leakage currents; technological forecasting; ITRS; MOSFET scaling; enhanced mobility; gate leakage current; high-k gate dielectric; metal gate electrode; nonclassical CMOS devices; polysilicon gate depletion; short channel effects; strained silicon channel; technological innovations; Circuits; Cost function; Electrodes; Leakage current; Logic devices; MOSFETs; Power dissipation; Power system reliability; Semiconductor materials; Technological innovation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
Type :
conf
DOI :
10.1109/ICSICT.2004.1434946
Filename :
1434946
Link To Document :
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