Strain engineering for hole mobility enhancement in p-channel field-effect transistors

A very promising strain engineering technique for enhancing the performance of p-channel transistors employs silicon-germanium (Si_1-y-Ge_y) source and drain stressors. To further exploit this method of strain engineering, the physical mechanism by which the SiGe source/drain (S/D) stressors contribute to the strain field needs to be understood. We evaluate the strain field due to the SiGe source/drain stressor, and examine two important strain components that affect transistor performance: the lateral compressive strain component and the vertical tensile strain component. The impact of transistor design parameters, such as the Ge mole fraction y in the stressors, the spacing L between stressors, the stressor depth d, and the raised stressor height h, on the strain field are investigated. Hole mobility enhancement larger than 30% is achievable with L = 50 nm and y = 0.15. More aggressive mobility enhancement targets may be achievable by reducing the stressor spacing and employing a stressor with a larger lattice mismatch with the Si channel.