Title :
Deep submicron embedded SRAM design issues
Author :
Natarajan, Sreedhar ; Romanovsky, Sergey ; Achyulhan, A.
Author_Institution :
MoSys Inc., Ottawa, Ont., Canada
Abstract :
This paper describes a few standby leakage reduction techniques in a 0.13μm SRAM and shows an improvement to 10pA/Cell through biasing techniques from the conventional 130pA/Cell. SNM and SER are also discussed briefly.
Keywords :
SRAM chips; integrated circuit design; leakage currents; biasing techniques; deep submicron embedded SRAM design; leakage reduction; Batteries; Leakage current; Low voltage; MOS devices; Noise level; Power dissipation; Random access memory; Read-write memory; Threshold voltage; Variable structure systems;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1435105
