TDCIV extraction of dopant-impurity concentration and oxide thickness in ultrathin gate oxide MOS transistors

A methodology is demonstrated for lateral position profiling of surface dopant-impurity concentration in the channel region and two extension regions using experimental tunnel direct-current current-voltage (TDCIV) curves on a pMOS transistor with W/L = 10μm/0.3μm fabricated by a factory 100nm technology. The methodology employs a zeroth-order and a first-order TDCIV model. Based on the zeroth-order model, constant oxide thickness, constant surface substrate-dopant-impurity concentration, and region length in each region were extracted. Then, using lateral dopant-impurity profile formulae in the first-order model to fit the TDCIV drain, source and basewell current data, the spatial variations of surface dopant-impurity concentration in the three regions are obtained.