Micro-architecture optimization of THUMP105 SOC implementation

Author

Sheng, Zhang ; Qian, Yang ; Runde, Zhou

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

Volume

2

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

1376

Abstract

At microarchitectural level this paper presents our research on performance-constraint problems for VLSI system design with IP and VC cores. With 32bit embedded and low-power processor THUMP105 as an example, delay complexity measure of control module, and signal noise ratio (SNR) of special managing request (SMR) signals were discussed to evaluate final performance and power consumption. Optimized results of THUMP105 indicated that the critical path delay was reduced by 46.8% at same supply voltage, which means that the lower supply voltage can be employed resulting in significant power saving with same performance constraints.

Keywords

VLSI; circuit optimisation; embedded systems; integrated circuit design; low-power electronics; microprocessor chips; system-on-chip; 32 bit; IP core; SMR signal; THUMP105 SOC implementation; VC core; VLSI system design; control module; critical path delay; delay complexity; delay estimation; embedded processor; low-power processor; microarchitecture optimization; performance-constraint problem; power consumption; signal noise ratio; special managing request; supply voltage; Delay; Energy management; Microarchitecture; Noise measurement; Power measurement; Signal processing; Signal to noise ratio; Very large scale integration; Virtual colonoscopy; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on

Print_ISBN

0-7803-8511-X

Type

conf

DOI

10.1109/ICSICT.2004.1436813

Filename

1436813