A generic interface modeling approach for SOC design

One of the key problems in IP-centric SOC design is integration between different IP cores. Since most IPs have different interface schemes and operation rules: they cannot smoothly communicate each other without any auxiliary glue logic. Furthermore, integration of IPs with different protocols is still a tedious error-prone task. To achieve the goal that make the most of IP reuse and smooth IP cores to communicate, this paper presents a generic language-independent interface modeling approach to assist interface synthesis. Given two different communication protocols, an algorithm is developed to generate synthesizable RTL code of interface subsystem on basis of the proposed interface model for IP integration. The novel algorithm can produce multi-language code such as Verilog, VHDL and SpeeC, which can be used as input for a synthesis tools. The proposed approach has been successfully integrated into our interface synthesis tool.