High-performance frequency dividers utilizing differential locking

The demand for low-power and high-speed wireless communication circuits is increasing towards the realization of a ubiquitous computing world. For high-performance wireless communication circuits, a frequency synthesizer with a phase-locked loop (PLL) and particularly the frequency divider used in the PLL must be improved. In this paper, to realize high-performance frequency dividers, a differential locking divider is introduced. Consequently, the successful fabrication of both a low-power divider and a high-speed divider is demonstrated and the differential locking divider is determined to be useful for obtaining a high-performance PLL.