Design and optimization of an integrated 1GHz PLL IP for microprocessors

Author

Bobxing, Zhao ; Huimin, Guo ; Hong, Zhou ; Chen Tie

Author_Institution

Inst. of Microelectron., Chinese Sci. Acad., Peking, China

Volume

2

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

1535

Abstract

A high speed phase locked loop is analyzed from the system point of view and different trade-offs in designing a stable low noise clock generator IP in microprocessors is discussed. A new design methodology for loop filter is presented to avoid using large on-chip capacitor in a standard logic CMOS process. Based on SMIC 0.18μm 1P4M logic process, the PLL operates up to 1.1 GHz, the root mean square of cycle-to-cycle jitter is 9.1 ps at 1 GHz output with 26.1 mW power consumption by post-layout simulation.

Keywords

CMOS logic circuits; circuit optimisation; integrated circuit design; microprocessor chips; phase locked loops; 0.18 micron; 1 GHz; 26.1 mW; 9.1 ps; SMIC 1P4M logic process; clock generator IP; cycle-to-cycle jitter; integrated PLL IP; large on-chip capacitor; loop filter; microprocessors; phase locked loop; post-layout simulation; standard logic CMOS process; CMOS logic circuits; Capacitors; Clocks; Design methodology; Design optimization; Filters; Microprocessors; Noise generators; Phase locked loops; Phase noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on

Print_ISBN

0-7803-8511-X

Type

conf

DOI

10.1109/ICSICT.2004.1436906

Filename

1436906