DocumentCode
436003
Title
A 5V 8b 40MSample/s pipelined analog-to-digital converter
Author
Liang, Xue ; Yanzhao, Shen ; Zhang Xiangimin
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Volume
2
fYear
2004
fDate
18-21 Oct. 2004
Firstpage
1559
Abstract
In this paper, a 5V 8b 40Msamples/s pipelined A/D converter is presented. The A/D converter contains seven stages and each stage realizes a resolution of 1.5bit. To reduce both linear and nonlinear errors, bottom-plate sampling, bootstrap and digital correction techniques are applied in ADC design. Accurate clocks are necessary for those techniques. Experiment results are obtained, with 1MHz input signal, the ADC acquired SNDR of 48.2dB SFDR of 58.2dB and 7.8 ENOB. The chip is fabricated in 0.35 μm N-well CMOS technology and occupies an area of 4 mm2.
Keywords
CMOS integrated circuits; analogue-digital conversion; 0.35 micron; 1 MHz; 5 V; 8 bit; N-well CMOS technology; bootstrap correction; bottom-plate sampling; digital correction; pipelined analog-to-digital converter; Analog-digital conversion; CMOS technology; Circuits; Clocks; Logic; Registers; Sampling methods; Signal resolution; Switches; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN
0-7803-8511-X
Type
conf
DOI
10.1109/ICSICT.2004.1436915
Filename
1436915
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