DocumentCode
43770
Title
Test and Repair Methodology for FinFET-Based Memories
Author
Harutyunyan, Gurgen ; Tshagharyan, Grigor ; Zorian, Yervant
Author_Institution
Synopsys Inc., Yerevan, Armenia
Volume
15
Issue
1
fYear
2015
fDate
Mar-15
Firstpage
3
Lastpage
9
Abstract
FinFET transistors are commonly acknowledged as the most promising technology able to play a crucial role to route the development of rapidly growing modern silicon industry. Embedded memories, based on FinFET transistors, lead to new defect types that can require new embedded test and repair solutions. To investigate FinFET-specific faults, the existing fault models and detection techniques are not enough because of the spatial structure of FinFET transistors. This paper presents the results of the comprehensive study carried out for FinFET-based memories based on a new fault modeling and test algorithm creation strategy. The proposed solution is validated on several real FinFET-based embedded memory technologies.
Keywords
MOSFET; maintenance engineering; semiconductor device testing; FinFET transistors; embedded memory technologies; fault modeling; modern silicon industry; repair methodology; spatial structure; test algorithm creation strategy; Circuit faults; FinFETs; Logic gates; Materials reliability; Resistance; SPICE; FinFET; defect; embedded memory; fault modeling; test algorithm;
fLanguage
English
Journal_Title
Device and Materials Reliability, IEEE Transactions on
Publisher
ieee
ISSN
1530-4388
Type
jour
DOI
10.1109/TDMR.2015.2397032
Filename
7027838
Link To Document