The level-3 trigger at the CDF experiment at Tevatron run II

A 96-channel TDC (time to digital converter) VME board was designed for the CDF detector in Tevatron collider run II at Fermilab. The features include: a custom ASIC (application specific integrated circuit) component that provides time measurements of signals from the various detector elements; a DSP (digital signal processor) that formats the digitized data sent to the data acquisition system; a built-in diagnostic system; a VME interface to read out the data and control the board configuration. This TDC board implements the CDF data acquisition and trigger protocols. The TDCs were designed initially to achieve 300 Hz readout rate. More than 400 of these TDCs provide 1 ns resolution timing for signal pulses from wire chambers, scintillator panels, and calorimeter towers. In addition, custom daughter boards connected to the TDCs provide data to the level-1 trigger system. We describe the functionality of the TDC boards and performance during run II operation.