A precise cyclic CMOS time-to-digital converter with low thermal sensitivity

In this paper, a precise cyclic CMOS time-to-digital converters (TDC) with low thermal sensitivity is proposed. Through compensation, the thermal sensitivity of the new cyclic time-to-digital converter is reduced dramatically. The proposed TDC possesses not only less thermal-sensitive resolution but also low cost and small chip size. The circuit was fabricated with TSMC 0.35 mum CMOS technology. The size of the circuit is 0.40 mm times 0.30 mm only. The experimental results show that a plusmn6% resolution variation of the new TDC was achieved within 0~100degC temperature range which is much better than plusmn25% of the original uncompensated version. The effective resolution is as fine as 58 ps at room temperature. The measurement rate is 33 kHz, at least.