Title :
SPIN-PAC: test compaction for speed-independent circuits
Author :
Shi, Feng ; Makris, Yiorgos
Author_Institution :
Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
Abstract :
SPIN-PAC is a static test compaction method for speed-independent circuits. We demonstrate how the test sets can be compacted by combining multiple consecutive test vectors within a test sequence into a vector pair of higher Hamming distance, and by eliminating or pruning independent test sequences. We discuss the exponential nature of optimally solving this problem, we propose an efficient algorithm to approximate it, and we evaluate its performance through experiments.
Keywords :
Hamming codes; asynchronous circuits; automatic test pattern generation; integrated circuit testing; logic testing; SPIN-PAC; higher Hamming distance; speed-independent circuits; static test compaction method; test sequence; test vectors; vector pair; Asynchronous circuits; Automatic test pattern generation; Change detection algorithms; Circuit faults; Circuit simulation; Circuit testing; Compaction; Delay; Fault detection; Silicon carbide;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466132
