Runtime leakage minimization through probability-aware dual-Vt or dual-Tox assignment

With process scaling runtime leakage current, when the circuit is operating, has become a major concern in addition to traditional standby mode leakage. In this paper we propose a new leakage reduction method that specifically targets runtime leakage current. We first observe that the state probabilities of nodes in a circuit tend to be skewed, meaning that they have either a high or a low value. We then propose a method that exploits these skewed state probabilities by setting only those transistors to high-K, (thick-oxide) that have a high likelihood of being off (on) and hence contributing significantly to the total runtime leakage. Accordingly, we also propose a library specifically tailored for the proposed approach, where V_t and T_ox assignment with favorably trade-offs under skewed input probabilities are provided. The optimization algorithm performs simultaneous sizing, V_t and T_ox assignment and shows substantial leakage improvement over probability-unaware optimization.