DocumentCode
438894
Title
A model of VLSI interconnect test based on boundary scan
Author
Jiangping, Yang ; Guixiang, Li ; Wanglei, Wang
Author_Institution
Dept. of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., China
Volume
1
fYear
2004
fDate
6-9 Dec. 2004
Firstpage
557
Abstract
Based on comprehensive analysis of the existing boundary-scan interconnect test, a new fault diagnosis model of VLSI interconnect test is established, which can ensure a comparatively higher testing speed, and solve the problems of symptom misjudgment and symptom aliasing effectively.
Keywords
VLSI; boundary scan testing; integrated circuit testing; VLSI interconnect test; boundary-scan interconnect test; symptom aliasing; symptom misjudgment; testing speed; Circuit faults; Circuit testing; Electronic equipment testing; Fault diagnosis; Integrated circuit interconnections; Integrated circuit technology; Matrix converters; Probes; Transmission line matrix methods; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Control, Automation, Robotics and Vision Conference, 2004. ICARCV 2004 8th
Print_ISBN
0-7803-8653-1
Type
conf
DOI
10.1109/ICARCV.2004.1468887
Filename
1468887
Link To Document