The impact of scaling down to deep-submicron on CMOS RF circuits

Recent papers reporting CMOS RF building blocks with very low current consumption have aroused much expectation in RF receivers using deep-submicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels for different feature sizes if robust designs are to be implemented. The need to match to 50Ω and to limit voltage gain in the input passive matching network is emphasized because it is often overlooked. At 1GHz, 0.25µm CMOS appears to be the threshold for robust, low-NF RF Front-ends with current consumption competive to today´s BJT implementations.