Practical low power design architecture for 256 Mb DRAM

This paper proposes a new circuit design architecture which is effective for low power, and high speed DRAMs. The characteristics of this schemes are: 1) a fish bone layout of the sub-decode-line in the divided word line (DWL) architecture, 2) a hierarchical bit line (BL) precharge power line and 3) a nonreset row block control and 4) a lowered BL precharge level in self refresh mode. A 256 Mb DRAM using these techniques was fabricated by a 0.25 µm CMOS process. An extremely low stand-by current (23 µA) and self refresh current (478 µA) were obtained.