A high speed SRAM macro for 0.35 µm low voltage SOI/CMOS gate arrays

A high-speed 2-port SRAM macro has been developed for 0.35µm SOI/CMOS gate arrays. The memory cell includes a new read buffer, which is composed of combinational gates, to reduce its area size and bit-line capacitances. The multiple read bit-line scheme was also adopted to reduce the access time in the SRAM macro. The test chips have been fabricated using both 0.35µm SOI/CMOS and bulk/CMOS processes. The access time of the 1.5K-bit (256word × 6bit) SOI SRAM was 2.6ns at 2.0V and 43% faster than that of the bulk counterpart. Even at the low supply voltage of 1.0V, the SOI SRAM operated at 6.4 ns.