Mismatch modelling for large area MOS devices

Investigations were made on mismatch effects in a bit cell for an analog-to-digital converter, fabricated in a 1.6µ/45nm CMOS process. The cell was designed to yield in a given bit resolution, considering the mismatch effects described by the well known law of area. It could be shown that large area MOS transistors are subject to a matching accuracy saturation effect, which makes it necessary to extend the mismatch model. An enhanced mismatch model is presented, which allows statistical simulation and prediction for both large area effects and for long distance effects between devices. The model was successfully verified by measurements and implemented into the statistical simulator GAME.