• DocumentCode
    439217
  • Title

    Low-power 200Msps, area efficient, 5-tap programmable FIR filter

  • Author

    Moloney, David ; O´Brien, Jerry ; O´Rourke, Eugene ; Brianti, Francesco

  • Author_Institution
    Silicon Systems Design Ltd., Dublin, Ireland
  • fYear
    1997
  • fDate
    16-18 Sept. 1997
  • Firstpage
    280
  • Lastpage
    283
  • Abstract
    A two-sample per cycle, programmable 5-tap, area efficient, FIR filter for hard-disk drive read-channels is presented. The design is optimised for low-power, achieving a figure of 5.16µW/Mhz[4] with a gate density of 2.3K, by a combination of algorithmic, architectural, circuit-level and layout techniques.
  • Keywords
    Algorithm design and analysis; Analog integrated circuits; BiCMOS integrated circuits; Centralized control; Design optimization; Finite impulse response filter; Hard disks; Low pass filters; Microelectronics; Pipelines;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1997. ESSCIRC '97. Proceedings of the 23rd European
  • Conference_Location
    Southampton, UK
  • Type

    conf

  • Filename
    1470918
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439217