A low-power, high-speed 0.25 µm GaAs D-FF

A design for low-power, high-speed static GaAs HJFET flip-flops (D-FFs) is discussed in detail. Four different types of delay latches based on NOR gates were designed. These latches were used to design 16 different types of D-FFs. A D-FF named "1POP" was chosen for fabrication using 0.25 µm GaAs HJFET technology. Experimental results showed that both the maximum operating clock frequencies (fmc) and power dissipations at fmcwere proportional to supply voltage (VD). The "1P0P" D-FF operated at fmcof 5.17 GHz on VD=0.6 V consuming only 2.03 mW that is the world\´s lowest power dissipation. Clear, wide eye openings were obtained in a fmcrange up to 7.15 GHz. Operating speeds were confirmed at an error rate of less than 10^-9with a (2⁹-1) pseudo-random signal.