• DocumentCode
    439238
  • Title

    Multilevel decoder-decision circuit for high bitrate ETDM transmission

  • Author

    Desrousseaux, P. ; André, Ph ; Meghelli, M. ; Konczykowska, A. ; Godin, J.

  • Author_Institution
    France Telecom - CNET-DTD, Bagneux Cedex, France
  • fYear
    1997
  • fDate
    16-18 Sept. 1997
  • Firstpage
    368
  • Lastpage
    371
  • Abstract
    An alternative to the classical binary format for ETDM transmission at high bitrate (over 20 Gb/s), the multilevel approach, is investigated. In this presentation, we deal with the reception end and compare different architectures for a multilevel decoder-decision circuit. Two designs are analysed in more details. A first realisation is presented, using an in-house InP/InGaAs 56 GHz DHBT technology; a comparison is done with a binary decision circuit processed at the same time. First conclusions about the multilevel format are presented.
  • Keywords
    Bit rate; Clocks; DH-HEMTs; Decoding; Detectors; Driver circuits; Indium gallium arsenide; Indium phosphide; Road transportation; Telecommunications;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1997. ESSCIRC '97. Proceedings of the 23rd European
  • Conference_Location
    Southampton, UK
  • Type

    conf

  • Filename
    1470940
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439238