A low-voltage, high-speed and low-power full current-mode video-rate CMOS A/D converter

This paper examines the feasibility of developing a full current-mode video-rate CMOS A/D converter (ADC), with 1V operation in mind in the future. The initial specification in the design stage was resolution greater than 8-bits, 20MHz clock frequency and 40mW of power dissipation from a 3V power supply. A fully current-mode pipeline ADC was created by using 0.6 µm CMOS process, resulting in 7-bit equivalent S/N, 20MHz clock speed, 3V operation and 100mW of power dissipation. It indicates the possibility of realizing a low-voltage video-rate ADC by using the full current-mode circuit approach.