• DocumentCode
    439245
  • Title

    A 103MHz open-loop full CMOS highly-linear sample-and-hold amplifier

  • Author

    Hadidi, Khayrollah ; Sasaki, Masahiro ; Watanabe, Tadatoshi ; Muramatsu, Daigo ; Matsumoto, Takashi

  • Author_Institution
    Urmia University, Urmia, Iran
  • fYear
    1997
  • fDate
    16-18 Sept. 1997
  • Firstpage
    396
  • Lastpage
    399
  • Abstract
    Based on a novel highly-linear cascode-driver CMOS source-follower buffer, we have designed a very high speed sample-and-hold circuit in a 0.8µm digital CMOS process. The circuit achieves -61dB THD at a sampling rate of 103MHz, while a 1.4Vp-p20 MHz input signal is applied. The high performance of the circuit is mainly due to its open-loop buffers and its fully differential structure.
  • Keywords
    CMOS process; CMOS technology; Capacitors; Clocks; Feedback circuits; Linearity; Sampling methods; Signal sampling; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1997. ESSCIRC '97. Proceedings of the 23rd European
  • Conference_Location
    Southampton, UK
  • Type

    conf

  • Filename
    1470947
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439245