DocumentCode
439253
Title
RFIC packaging and test: How will we cut costs?
Author
Strid, Eric W.
Author_Institution
Cascade Microtech, Inc., United States
fYear
1998
fDate
22-24 Sept. 1998
Firstpage
51
Lastpage
54
Abstract
The current state of the art and trends in packaging and engineering and production testing of RFICs are surveyed. Existing and new strategies for long-range improvements in RFIC packaging and testing costs are compared. Increasing integration levels, chip-scale packaging, earlier testing, and parallel testing will be future themes in RFIC assembly and test.
Keywords
Circuit testing; Costs; Integrated circuit modeling; Integrated circuit testing; Packaging machines; Probes; Production; Productivity; Radio frequency; Radiofrequency integrated circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
Type
conf
DOI
10.1109/ESSCIR.1998.186206
Filename
1470963
Link To Document