DocumentCode
439265
Title
16-Gbit/s measurements on a 0.8- µm CMOS sub-sampling circuit
Author
Johansson, H.O. ; Svensson, C.
Author_Institution
Linköping University, Linköping Sweden
fYear
1998
fDate
22-24 Sept. 1998
Firstpage
124
Lastpage
127
Abstract
Measurements have been done on a 0.8-µm CMOS sub-sampling circuit where a 16-Gbit/s data stream was successfully sampled. The input bit-rate was limited by the test setup. SPICE simulations on extracted layout with included bondwire inductances show correct sampling of 25-Gbit/s data streams. The circuit uses aggressively designed sampling switches and input pads. The package for the circuit is co-designed with the chip to attain high input-bandwidth.
Keywords
Apertures; Capacitance; Circuits; Clocks; MOS devices; Sampling methods; Signal design; Switches; Threshold voltage; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1998. ESSCIRC '98. Proceedings of the 24th European
Conference_Location
The Hague, The Netherlands
Type
conf
DOI
10.1109/ESSCIR.1998.186224
Filename
1470981
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