An area-efficient circuit concept for dynamical conflict management of N-port memories with multi-GBit/s access bandwidth

N-port memories are attractive, because in comparison to 1-port memories a large access bandwidth without latency is possible even at low clock frequencies. However, dynamical management of unavoidable access conflicts becomes necessary. We present an area-efficient conflict-management concept, which can be generally applied for N-port memories, and a circuit implementation in 0.5µm CMOS technology. Small circuit sizes (≤0.052 mm²) and short delay times (≤1.1ns) are achieved with best-case as well as worst-case conflict-regulation algorithms for a hierarchical 4-port memory with low (<0.05) access-rejection probability. The small circuit sizes enable applicability of the new hierarchical N-port memory architecture [1] for storage capacities down to 4Kbit. Multi-GBit/s latency-free access to a 4-port memory is already possible at clock frequencies well below 100MHz.