Analog VLSI implementation of early vision edge detection with noise suppression and image segmentation

We present an analog VLSI implementation of a new multiplexed two-layer parallel resistive network for early vision edge detection with noise suppression and image segmentation. One layer of the network is multiplexed to implement both Gaussian filtering and image segmentation by using the extracted edge information to control its horizontal resistors. The vertical resistors are realized by linearized operational transconductance amplifiers (OTA) with dual outputs to feed both network layers from a single input. The horizontal resistors are realized with single MOS transistors. Their gates are supplied with voltages higher than the supply voltage VDD., which are generated on-chip by a charge pumping circuit to ensure operation in the linear region while using small transistor dimensions. For edge detection, a new method for zero-crossing determination was implemented using an analog multiplier and a current comparator. To suppress incorrectly detected edges caused by noise, a special chopper circuit was applied.