A mixed-signal ASIC with embedded DSP core for power metering application

This paper presents a class 0.5, three phase power metering circuit designed in 0.6µm CMOS process. A sigma delta based analog front-end combined with hard wired digital filters is used for A/D conversion of the current and voltage signals. The computation of all parameters required for a third generation power metering system, is performed by the configurable DSP core GEPARD. Cost considerations call for the integration of a high precision analog front-end together with a DSP core, RAM and ROM on the same substrate. The ASIC also provides flexibility to the power meter manufacturer, who can adjust to country specific requirements by changing the DSP code in the program ROM. In fact, the basic concept of the ASIC is suitable to a wide range of applications.