A 1.3 GOPS parallel DSP for high performance image processing applications

In this paper, a programmable DSP for real time image processing is presented that combines the concepts of VLIW and SIMD with a high utilization of parallel resources on instruction level and data level. The SIMD approach has been extended with autonomous instruction selection capabilities (ASIMD), which offers to control four parallel datapaths with low area overhead. The memory concept is adapted to image processing requirements and follows two basic rules: Shared data have to be accessed regularly in shape of a matrix and are stored in the Matrix Memory. As soon as data are accessed irregularly, they are stored in the private cache memories. The Matrix Memory allows parallel, conflict-free access from all datapaths in a single clock cycle. A first prototype of the DSP with four datapaths achieves 1.3 GOPS performance at 66 MHz, using a 0.5µm CMOS technology.