Investigation on low voltage, low power silicon bipolar design topology for high speed digital circuits

This paper investigates a bipolar design topology which is suitable to operate from a voltage supply well below 1.5-V, while maintaining the ability of high frequency operation. We applied the topology in the design of different divide-by-4 circuits, which featured slightly changed component architecture. Measurements have shown operation at 1.0-V supply voltage and up to 4.2- GHz input frequency, and at 1.5-V up to 6-GHz. The power consumption is approximately 0.3-mW/latch and 1.2-mW/latch, respectively.