• DocumentCode
    439378
  • Title

    A low-jitter mixed DLL for high-speed DRAMs

  • Author

    Jae Joon Kim ; Beomsup Kim ; Sangbo Lee ; Soo-In Cho

  • Author_Institution
    KAIST, Taejon, Korea
  • fYear
    1999
  • fDate
    21-23 Sept. 1999
  • Firstpage
    134
  • Lastpage
    137
  • Abstract
    A mixed delay-locked loop adapting digital delay line structure for low-power, fast-locking characteristics and analog tuning technique for low-jitter performance is presented. The mixed DLL is fabricated in 3.3V 0.6-µm triple-metal CMOS process, and the area is 0.45mm2. Measured rms jitter is 6.38ps and power consumption is 33mW at 200MHz, 3.3V supply.
  • Keywords
    Circuits; Clocks; Delay effects; Delay lines; Jitter; Mirrors; Monitoring; Propagation delay; Random access memory; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European
  • Conference_Location
    Duisburg, Germany
  • Type

    conf

  • Filename
    1471114
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439378