A 500MS/sec -54dB THD S/H circuit in a 0.5 µm CMOS process

Based on an open-loop architecture and a highly linear buffer, a S/H was implemented in a 0.5µm CMOS process. Its differential architecture allows a single NMOS device to do sampling for both halves of the circuit, eliminating any error of otherwise mismatched sampling switches. The circuit achieved a performance of 500MS/sec, -54dB THD for a 50MHz 1Vp-p input. The THD was reduced to -74dB for a 10MHz, 1.5Vp-p at 100MS/sec. Input range of the circuit is 2.0Vp-p. Note that intentionally large devices were used in the circuit to minimise parasitic capacitor effects on the circuit during testing. For use inside an ADC, the device sizes can be scaled down by a factor of 4. Then the power consumption would be reduced to 5.5mW from existing 21 mW. The device requires a 3.3 Volt supply and an area of 0.15mm²(which can be reduced to 0.04mm²after scaling down).