A 15-bit pipelined floating-point A/D converter

A 15-bit switched-capacitor pipelined floating-point A/D converter (FADC) has been designed with a 5-bit exponent and a 10-bit mantissa. The exponent value is established by a 3-stage pipelined variable gain amplifier, while the mantissa is determined with a 10-bit uniform pipelined A/D converter. An experimental prototype of the converter has been implemented in a 0.5-µm CMOS technology. It achieves a dynamic range of 15 bits at a conversion rate of 20Msamples/sec with a total power dissipation of 380mW.