Distributed active clock network

A distributed clock network can alleviate problems of skew and jitter in GHz-clock-speed microprocessors. A proof-of-concept chip fabricated in a 0.6µm process achieves 354MHz operation of 4 phase-locked oscillators. Supply noise insensitive, current controlled oscillators; nonlinear, modelock-resistant phase detectors; and the loop filters needed for multiple interconnected PLLs are integrated on chip, with a total area per PLL of less than 0.02mm².