A low power reconfigurable 12-tap FIR interpolation filter with fixed coefficient sets

A parameterizable architecture of a low power FIR interpolation filter with reconfigurable coefficient sets for timing phase alteration is presented. For the application in a handheld ultrasound scanner, the filter has been optimized for lowest power dissipation on all levels of CMOS design from system down to physical layout level. The architecture is well suited for a datapath generator design offering full-custom performance at lowest design effort. A test chip integrating a 6/12-tap filter has been realized in a 0.5-µm CMOS technology for a clock frequency of 40 MHz featuring a power dissipation as small as 0.9 mW per tap.