DocumentCode
439483
Title
Iterative self-timed multiplier with early completion
Author
Kim, Do-Wan ; Jeong, Deog-Kyoon
Author_Institution
Seoul National University, Korea
fYear
2000
fDate
19-21 Sept. 2000
Firstpage
109
Lastpage
112
Abstract
We designed a self-timed multiplier with DCVSL. The multiplier supports 32-bit integer multiplication of both signed and unsigned operands. It incorporates an early completion scheme for fast operation. We proposed a 4- phase handshake circuit that fits well with DCVSL. We implemented the designed multiplier with 0.25µm CMOS technology. The performance of the multiplier varies between 20.5M and 128M multiplications per second depending on the inputs. The size of core multiplier is 700 µm × 350 µm.
Keywords
Circuits; Clocks; Ear; Independent component analysis; Latches; Logic; Protocols; Reactive power; Signal generators; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
Conference_Location
Stockholm, Sweden
Type
conf
Filename
1471225
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