Title :
Iterative self-timed multiplier with early completion
Author :
Kim, Do-Wan ; Jeong, Deog-Kyoon
Author_Institution :
Seoul National University, Korea
Abstract :
We designed a self-timed multiplier with DCVSL. The multiplier supports 32-bit integer multiplication of both signed and unsigned operands. It incorporates an early completion scheme for fast operation. We proposed a 4- phase handshake circuit that fits well with DCVSL. We implemented the designed multiplier with 0.25µm CMOS technology. The performance of the multiplier varies between 20.5M and 128M multiplications per second depending on the inputs. The size of core multiplier is 700 µm × 350 µm.
Keywords :
Circuits; Clocks; Ear; Independent component analysis; Latches; Logic; Protocols; Reactive power; Signal generators; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
Conference_Location :
Stockholm, Sweden