12 bit low power fully differential switched capacitor non-calibrating successive approximation ADC with 1MS/s

Based on a conventional successive approximation ADC architecture a new and faster solution is presented. The input structure of the new solution consists of transmission gates and capacitors only and there is no need for any active element. A switching circuit is implemented to allow a wider input voltage range of the ADC. Together with a self timed comparator the power consumption is noticeably reduced while at the same time the sampling rate is doubled. Smaller input and reference capacitances reduce the requirements on the input and reference sources, respectively. Additionally, a clock duty cycle independent control logic improves the applicability of the converter cell especially for systems on chip. Results of measurements confirm the theoretical improvements.