DocumentCode :
439503
Title :
A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM wireless receivers
Author :
Yan, William Shing-Tak ; Luong, Howard Cam
Author_Institution :
Hong Kong University of Science and Technology, Kowloon, Hong Kong
fYear :
2000
fDate :
19-21 Sept. 2000
Firstpage :
200
Lastpage :
203
Abstract :
A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.5-mm CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm2and consumes a low power of 34 mW. The measured phase noise of the dual-loop synthesizer is -121.8 dBc/Hz at 600-kHz frequency offset. The measured spurious levels are -79.5 and -82 dBc at 1.6 MHz and 11.3MHz offset, respectively.
Keywords :
CMOS technology; Frequency conversion; Frequency measurement; Frequency synthesizers; GSM; Noise measurement; Oscillators; Phase measurement; Phase noise; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
Conference_Location :
Stockholm, Sweden
Type :
conf
Filename :
1471246
Link To Document :
بازگشت