A novel high speed low power logic family: Race logic

A new logic family, Race Logic, is proposed for high speed and low power applications. Race Logic does not use transistors but utilise timing difference between two racing signals to implement boolean logic operations. Because the number of transistors is very small compared to conventional logic styles, delay time from clock to output is very small and the power consumption is also minimized. Various kinds of combinational circuits are simulated, and a 64bit carry look-ahead adder is fabricated using Race Logic.