DocumentCode
439556
Title
Skewed CMOS: Noise-immune high-performance low-power static circuit family
Author
Solomatnikov, Alexandre ; Somasekhar, Dinesh ; Roy, Kaushik
Author_Institution
Purdue University, West Lafayette, IN
fYear
2000
fDate
19-21 Sept. 2000
Firstpage
423
Lastpage
426
Abstract
In this paper, we present a noise-immune high-performance static circuit family called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and they are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power and dynamic noise immunity. Comparison between skewed and Domino circuits on a 0.25µm 700 MHz 16 × 16 bits pipelined multiplier shows superior properties of skewed circuits over Domino in terms of clock power dissipation and peak current consumption.
Keywords
CMOS logic circuits; CMOS technology; Circuit noise; Delay; Logic circuits; Logic gates; Low voltage; MOS devices; MOSFETs; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
Conference_Location
Stockholm, Sweden
Type
conf
Filename
1471300
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