A 1.8 GHz CMOS Δ Σ fractional-N synthesizer

A 1.8 GHz ΔΣ fractional-N frequency synthesizer is presented. The digital synthesizer part is integrated together with an LC- VCO, a 35 kHz dual-path loop filter and a 16 modulus prescaler in 0.25µm CMOS technology. The zero-dead zone phase detector is optimized towards linearity and spurious suppression. The influence of MASH and multi-bit, single-loop ΔΣ modulators on the synthesizer performance is simulated and experimentally verified. The synthesizer consumes 35 mA from a single 2 V power supply, 25 mA of which is due to the integrated VCO. The measured phase noise is lower than -120 dBc/Hz at 600 kHz. Reference spurs are below - 75 dBc, while the fractional spur level is lower than - 100 dBc.