A 7-GHz 1.8dB NF CMOS low noise amplifier

A 7-GHz low noise amplifier (LNA) was designed and fabricated using 0.25µm-CMOS technology. A cascode configuration with a dual-gate MOSFET and shielded pads are adopted to improve the gain and the noise performances. The effects of the dual-gate MOSFET and the shielded pads are discussed quantitatively. The associated gain of 8.9dB, minimum noise figure of 1.8dB and input-referred 3rd-order intercept point of +8.4dBm were obtained at 7GHz. The LNA consumes 6.9mA from a 2.0V supply voltage. These measured results indicate the feasibility of a CMOS LNA with the appropriate techniques for low-noise and high-linearity applications over 5GHz.