A CMOS log image sensor with on-chip FPN compensation

This paper describes a logarithmic image sensor in CMOS technology by using photodiode in photovoltaic mode. Thanks to this pixel design, an electronic dark image reference can be obtained for each pixel readout and a fixed pattern noise (FPN) compensation can be easily done by on-chip analog circuits. A 160×120-pixel prototype circuit in a standard 0.8µn DPDM CMOS technology will be described. This prototype chip has demonstrated low FPN, high dynamic range and high sensitivity at low light condition (<1lux).