A general-purpose CMOS vision chip with a processor-per-pixel SIMD array

The paper discusses the architecture and implementation of a new SIMD focal-plane processor array integrated circuit. The chip employs switched-current "analogue microprocessors" as processing nodes in a digital-like massively parallel computer architecture. Using analogue processing elements allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21×21 SCAMP vision chip is fabricated in a 0.6µm CMOS technology and achieves a cell size of 98.6µm×98.6µm. The approach is compared with state-of-the-art vision chips build using digital SIMD arrays and CNN-based processors. Experimental results are presented.