VLSI implementation of a high performance and low power 32-bit multiply-accumulate unit

A high performance and low power 32-bit multiply-accumulate unit (MAC) is described in this paper. The fast mixed length-encoding scheme used in the MAC leverages the advantage of a 16-bit encoding scheme without adding extra delay to the faster four-stage Wallace Tree of a 12-bit encoding scheme. A mixture of static CMOS logic and complementary pass-gate logic (CPL) was used to achieve the high speed and still meet the low power goal. Several power saving techniques were also implemented in this MAC.